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REV. 0
EVAL-AD1852EB
–6–
MODCLK
/Clocks in serial mode codes
MODSTM
/Serial mode code stream from CPU
pin 40;
/
pin 37;
/
“OUTPUTS ———————————————————————————————————
// TDO pin 29; //JTAG O/P
M0, M1, M2 pin 3, 2, 18 istype ‘com’; //DIR Mode Select
IDPM0, IDPM1 pin 35, 36 istype ‘com’; //DAC Mode Select
MCLK, BCLK, LRCLK pin 30, 32, 33 istype ‘com’; //DAC Digital Data
SDATA pin 31 istype ‘com’;
MCLKO pin 23 istype ‘com’; //Ext MCLK Drive
DEEMPH pin 25 istype ‘com’; //DAC Deemphasis Control
NLVERF, NLZL, NLZR, NLDEEMPH pin 11, 21, 22, 20 istype ‘com’; //LED Status Drive
ESDATA, ELRCLK, EBCLK pin 43, 42, 41 istype ‘com’; //External Data I/Os
// Registers for delaying the data in RJ and DSP modes
// such that it is output in the correct format
// to match the signal requirements for the AD1852.
“NODES
QA, QB, QC, QD, QE, QF node istype ‘reg, buffer’;
QG, QH, QI, QJ, QK, QL node istype ‘reg, buffer’;
Q20, Q24
node istype ‘reg, buffer’;
QDSP
node istype ‘reg, buffer’;
// Shift register for reading/holding mode codes
// streaming in from CPU’s LabView control program.
QM0, QM1, QM2, QM3 node istype ‘reg, buffer’;
“MACROS // S5 position 4, External Mode Control
XMODC = (!SLCT_C & SLCT_B & SLCT_A);
//EQUATIONS
// S5 position 0, LabView selection 1, LJ, Invert DIR BCLK
LJ = ( SLCT_C & SLCT_B & SLCT_A)
# ( XMODC & ( (!QM3 & QM2 & !QM1 & QM0)
# ( QM3 & !QM2 & QM1 & !QM0) ) );
// S5 position 1, LabView selection 2, I2S
I2S = ( SLCT_C & SLCT_B & !SLCT_A)
# ( XMODC & ( (!QM3 & QM2 & QM1 & QM0)
# ( QM3 & QM2 & QM1 & !QM0)
# ( QM3 & QM2 & !QM1 & QM0)
# ( QM3 & !QM2 & QM1 & QM0) ) );
// S5 position 2, LabView selection 4, RJ_24, 24-Bit
RJ_24 = ( SLCT_C & !SLCT_B & SLCT_A)
# ( XMODC & ( (!QM3 & !QM2 & !QM1 & QM0)
# (!QM3 & !QM2 & QM1 & !QM0)
# (!QM3 & QM2 & !QM1 & !QM0)
# ( QM3 & !QM2 & !QM1 & !QM0) ) );
// S5 position 3, LabView selection 3, DSP WSync, Delay SDATA
DSP = ( SLCT_C & !SLCT_B & !SLCT_A)
# ( XMODC & (!QM3 & !QM2 & !QM1 & !QM0) );
// LabView selection 5, RJ_20, 20-Bit
RJ_20 = ( XMODC & ( (!QM3 & !QM2 & QM1 & QM0)
# (!QM3 & QM2 & QM1 & !QM0)
# ( QM3 & QM2 & !QM1 & !QM0)
# ( QM3 & !QM2 & !QM1 & QM0) ) );
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